This invention relates to systems and methods for overlay shift determination, and in particular, to systems and methods for determining the magnitude and direction of an error in the alignment of at least one first layer with at least one second layer of a semiconductor device.
Semiconductor devices are manufactured with a plurality of different layers and a plurality of different processing steps, such as, for example, masking, resist coating, deposition and etching. During the semiconductor manufacturing process, many materials are provided on the semiconductor device and portions of the provided materials are removed by etching, for example, in order to form elements of the integrated circuit. For example, circuit elements are formed using patterned masks which expose and protect respective regions of various layers to form an integrated circuit. These patterned masks, for example, should be substantially, and ideally completely, aligned with the respective layer.
Ideally the respective layers and/or patterned masks of an integrated circuit, for example, are perfectly aligned. However, perfect alignment is difficult, and nearly impossible to achieve. Errors in the alignment of one layer with another layer during the manufacturing process of semiconductor devices can occur for a wide-variety of reasons. For example, errors made during the manufacturing process may occur as a result of alignment noise, stage scanning problems, lens distortions, and wafer stage inaccuracies.
The performance of the semiconductor device, however, depends on the proper alignment of the patterned masks with each of the layers forming the semiconductor device. As integrated circuits become smaller and smaller the proper alignment between layers becomes even more important. If the layers and/or masks for forming the semiconductor device and the integrated circuits formed thereon are not aligned properly, the semiconductor device may fail to operate properly, if at all.
There are a variety of known methods for detecting the misalignment between layers of semiconductor devices. By way of example, it is known to use resistance based alignment for magnetoresistive elements, where the sheet resistivity of each of the two alignment test structures is used to detect the misalignment of the elements. However, these types of designs require large structures and are dependent on processing variations. Other methods include ways to determine if the openings located in the contact layer and the interconnect layer are misaligned. However, these methods do not determine the direction or the magnitude of the misalignment.
In still other methods, mask-alignment test structures are used for measuring the alignment of superimposed elements formed on and within a semiconductor element. In order to determine the magnitude and extent of misalignment in both the X and Y directions, for example, in these methods, it is necessary to have four of the structures disclosed. Further, in order to determine the magnitude and extent of the misalignment in accordance with such methods approximately sixteen steps and seven probe pads are required in the case where a decoder is not used and approximately four steps and ten probe pads are required in the case where a decoder is used. Thus, such devices are large in size and/or time consuming due to the number of steps required to determine the magnitude of the misalignment. This is time consuming and costly. It is also known to use optical methods to determine error in misalignment. However, optical methods for determining error in misalignment are generally slower than electrical test structures.